Free / Grades 9-10; choose by readiness
Logic Design Studio
How can I show that a tiny adding machine works for every allowed input?
5 flexible sessions / about 215 minutes including practice / computing, mathematical checks, explanation and design
Suggested rhythm: two sessions a week for three weeks, with the last meeting for the demonstration. Pause or spread out the work as needed. There is no deadline.
Reading, watching and paper activities are free. Parents and instructors can save a collection; scheduling it for a student requires Plus or Lifetime. No upload is required.
Before you begin
Add whole numbers through six, read a table and follow named intermediate steps. Session 1 reviews AND, inclusive OR and XOR. Binary place values are taught here; speed and prior hardware experience are not requirements.
Paper logic, not electrical construction. No batteries, wires, components, outlets or real devices are needed. Do not connect or open electrical equipment. These ideal bits have no specified voltage, delay or power rating. Use only paper and the browser; no download, upload, purchase or public presentation is required.
Materials
- 5 sheets per learner: Project journals
Print the five pages or copy the tables into a notebook.
- 2 sheets per learner: First design and revised explanation
Keep the first version on scrap paper; do not erase it when revising.
- 1 per learner: Pencil
Point, dictate or use an accessible writing tool.
- 1 shared: Browser with transcripts
Read lesson chapters together. The journals provide a paper alternative to game controls.
Choose the support that fits
- More support: use large 0/1 cards, read gate rules aloud and trace one named signal at a time. Keep the weighted-total check separate from the output calculation.
- More challenge: explain why the sixteen final cases cover the whole stated input domain but do not establish real-world timing, electrical safety or wider number formats.
- Access options: replace drawings with labeled connection lists and spoken explanations. A partner may record the learner's trace. Neatness, typing speed and color recognition are not criteria.
What good evidence looks like
- State that each input number has two unsigned bits and the first carry-in is zero.
- Label the gate rules, Sum and Carry outputs, place values and each carry connection.
- Predict from ordinary arithmetic before tracing the design.
- Test all sixteen allowed input pairs, including zero and a final carry.
- Keep an earlier design, explain a correction or justified choice, and name a limit of the evidence.
These are discussion criteria, not a new automatic score. Existing lesson and worksheet records keep their own subjects. Checking off a planned task does not demonstrate mastery or add a second grade.
Session 1 / about 35 minutes
A rule needs all its cases
Goal: Distinguish gate outputs and explain why a few matching examples do not prove two rules equivalent.
Preparation / about 7 minutes of adult support: Have journal 1 and a first-design sheet ready. Keep that first explanation for the final session. Read XOR as exclusive OR.
A bit is 0 or 1. AND is 1 only when both inputs are 1. Inclusive OR is 1 when at least one input is 1. Two-input XOR is 1 when the inputs differ. Test each rule separately; the word OR is not permission to swap rules. Two output places can represent a total: the left place counts twos and the right place counts ones. Binary 10 is two, not ten. A gate does not gain extra points for sounding confident.
Predict which row can distinguish OR from XOR, then complete every row. Why would testing only unequal inputs hide the difference?
- Check every logic case / about 8 minutes
- Programming Basics: Combine Boolean Conditions / about 10 minutes
- Compare three gate rules / about 17 minutes
Fun fact: Two independent bits have four possible input pairs. A table with four different pairs can cover the entire domain, unlike four repeats of one pair.
S3U / Logic Design Studio / Journal 1 of 5
Four different cases, not four guesses
For each A/B input pair, compute AND, inclusive OR and XOR separately. Record your prediction about the differing row before completing the table. Keep a first explanation on another sheet.
| A/B | AND | OR | XOR |
|---|---|---|---|
| 01 | |||
| 11 | |||
| 00 | |||
| 10 |
Which row disproves the claim that OR and XOR always agree? Explain, not just name it.
Explain binary 01 and 10 using their place values. Why must output labels stay attached?
Session 2 / about 40 minutes
Keep the whole total
Goal: Build a half-adder specification and check both outputs against ordinary addition.
Preparation / about 8 minutes of adult support: Have journal 2 ready and keep a separate diagram or labeled connection list. Name Carry and Sum before filling output bits.
For two input bits, Sum = A XOR B and Carry = A AND B. Check A + B = 2 x Carry + Sum. The output named Sum is only the ones bit, not the whole answer. For input 11 the two gates give Carry 1 and Sum 0, which represent two. Keeping only Sum would lose two; two bits cannot squeeze themselves into a one-bit suitcase.
Compare the rows 00 and 11. Can the Sum bit alone tell them apart? Then ask whether Carry and Sum can both be 1 for this two-input device.
- Add bits and keep the carry / about 9 minutes
- Check a Half Adder's Two Outputs / about 10 minutes
- Specify and check my half adder / about 21 minutes
Fun fact: Swapping the two half-adder inputs leaves both outputs unchanged. Their labels differ, but their weights in the total are equal.
S3U / Logic Design Studio / Journal 2 of 5
Two outputs, one conserved total
Predict A + B before tracing the half-adder gates. Read the result as Carry then Sum. Include every input pair in the supplied order; show 2 x Carry + Sum as a separate check.
| A/B | Predicted total | Carry / Sum | Weighted check |
|---|---|---|---|
| 10 | |||
| 00 | |||
| 01 | |||
| 11 |
A shortcut uses OR instead of XOR for Sum. Find a failing input and the false total it produces.
Does output 01 identify a unique input pair? Use your table to explain.
Session 3 / about 40 minutes
Let a carry come in
Goal: Trace a full adder and distinguish a carry arriving from a smaller column from a carry leaving for a larger one.
Preparation / about 9 minutes of adult support: Use journal 3. Keep the rules visible: X=A XOR B; G=A AND B; P=X AND C; Sum=X XOR C; Carry=G OR P. C means carry-in.
A full adder includes three equal-weight input bits: A, B and C. First find X and G, then use X with C for P and Sum. Carry combines G and P. For the worked input 101, X=1, G=0 and P=1, so Sum=0 and Carry=1. Check A+B+C=2 x Carry+Sum. Incoming and outgoing carry have different jobs; matching names do not force matching values.
Test a proposed Carry=G-only shortcut with an input where C is 1. Which intermediate signal tells you what the shortcut lost?
- Check Carry-In and Carry-Out / about 10 minutes
- Trace all eight full-adder inputs / about 22 minutes
- Explain an incoming-carry counterexample / about 8 minutes
Fun fact: Three independent input bits have eight possible triples. A full adder can produce Carry 1 and Sum 1 because its three inputs can total three.
S3U / Logic Design Studio / Journal 3 of 5
The extra input has a job
Rules: X=A XOR B; G=A AND B; P=X AND C; Sum=X XOR C; Carry=G OR P. C is incoming. For each A/B/C row write X/G/P, then Carry/Sum and its total 2 x Carry + Sum. Check against A+B+C.
| A/B/C | X / G / P | Carry / Sum and total |
|---|---|---|
| 000 | ||
| 001 | ||
| 010 | ||
| 011 | ||
| 100 | ||
| 101 | ||
| 110 | ||
| 111 |
Choose a row that defeats Carry=G alone. Which value supplies the missing carry?
Give one case with C-in 1 but Carry-out 0, and one with C-in 0 but Carry-out 1.
Session 4 / about 50 minutes
Pass the carry to the next place
Goal: Join two full-adder columns and retain the last carry as a third result bit.
Preparation / about 9 minutes of adult support: Have journal 4 and the draft design. Use columns labeled ones and twos, then leave a separate result box labeled fours. Game controls are optional.
Start at the ones column with C-in 0. Pass its Carry-out into the twos column as that column's C-in. The twos Carry-out becomes the fours result bit. For binary 10+01, the ones column gives 1 without carry; the twos column also gives 1 without carry, so the result is 011, meaning three. Keep the leading zero while checking the three-place design. A carry that falls off the page is missing data, not tidying up.
Ask which signal connects the columns and why the calculation starts on the right. How would discarding the last carry change the meaning of an output?
- Signal Station / about 20 minutes
- Trace four two-column additions / about 20 minutes
- Label my carry connection / about 10 minutes
Fun fact: The largest sum of two unsigned two-bit numbers is six. Three result bits can hold that total; two result bits cannot.
S3U / Logic Design Studio / Journal 4 of 5
One carry, a new place value
Initial C-in is 0 for each fresh addition. Record each column's A/B/C input triple, then the final three-bit result in fours/twos/ones order. Predict the ordinary total first on scrap paper.
| Binary inputs | Ones A/B/C | Twos A/B/C | Result |
|---|---|---|---|
| 00 + 00 | |||
| 01 + 01 | |||
| 01 + 11 | |||
| 11 + 11 |
For 01 + 11, follow the carry through both columns. What value would be lost if the final bit were dropped?
Compare the logical model with real hardware. Name one thing these calculations do not measure or guarantee.
Session 5 / about 50 minutes
Test, repair and defend the design
Goal: Demonstrate complete input coverage, a reasoned revision and the limits of an ideal two-bit adder.
Preparation / about 10 minutes of adult support: Bring all journals and the first design. Use a second sheet for the revised explanation. A private self-demonstration is acceptable; inviting a connected adult is optional.
Write the specification before testing: two unsigned two-bit numbers, initial carry zero, and a three-bit result. Predict every output from ordinary addition, then independently trace your connected gates and compare. An exhaustive test covers all allowed pairs, not all possible devices. If a result differs, keep the old trace, identify the first wrong intermediate signal and retest after repair. A correct design needs an explanation, not an invented mistake to fix.
Offer this faulty design: both columns work, but only their two Sum bits are displayed. Find a case that passes and a case that fails. Explain why keeping the final Carry repairs the specification.
- Predict and trace all sixteen cases / about 25 minutes
- Demonstrate my repaired or justified design / about 15 minutes
- Keep my design reflection / about 10 minutes
Fun fact: Four choices for the first two-bit number and four for the second give sixteen ordered input pairs. Reversing the operands is another test even when addition gives the same total.
S3U / Logic Design Studio / Journal 5 of 5
My design and complete evidence
Rows give the first binary number; columns give the second. Initial carry is zero. Write the three-bit result in each cell after predicting, tracing and comparing. Keep any mismatch and repair on your design sheet.
| First / second | 00 | 01 | 10 | 11 |
|---|---|---|---|---|
| 00 | ||||
| 01 | ||||
| 10 | ||||
| 11 |
Which input exposes a design that drops the final Carry, and which passes anyway? Explain the repair.
What changed in your explanation, or what justified an original choice? Name a model limit and a next question.
What changed in your explanation?
Show your evidence, explain one revision, and choose a question to investigate next. You can keep everything on paper.
Optional: record actual offline learning in Learning Records. Keep reported minutes separate from website time. For an assigned pack, use your existing daily tasks; this page does not award additional completion credit.